New PDF release: Algorithmically Specialized Parallel Computers

By Lawrence Snyder, Leah H. Jamieson, Dennis B. Gannon

ISBN-10: 0126541302

ISBN-13: 9780126541304

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Architecture The architecture used here is a linear array of 0(lgN) identical processing elements, each with their own private memory attached. Processor Pi has memory capable of storing a single tree node, and each processor Pit 1 < i

2. High-Level Design Description This section of our report discusses the high-level design issues involved in the RESST project. The RESST sorting algorithm is presented, and the overall structure and data flow of the RESST chip are described. 1. A Hardware Sorting Algorithm The algorithm that we chose to use in the design of RESST is a parallel bubblesort algorithm. Let n be the number of items to be sorted, where each item has a fixed-length key (that is, key length is independent of n). Let N be the number of items that the chip can hold.

6. 7. 8. 9. 10. 11. 12. 13. R. W. Floyd and J. D. Ullman, "The Compilation of Regular Expressions into Integrated Circuits," JACM 29(3) pp. 606-622 (July 1982). D. Johannsen, "Bristle Blocks: A Silicon Compiler," Proc. , pp. 310-313 (June 1979). R. E. Ladner and M. J. Fischer, "Parallel Prefix Computation," JACM 27(4) pp. 831-838 (Oct. 1980). C. Mead and L. Conway, Introduction to VLSI Systems, AddisonWesley (1980). S. P. Reiss and J. E. Savage, "SLAP - A Methodology for Silicon Layout," frocs.

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Algorithmically Specialized Parallel Computers by Lawrence Snyder, Leah H. Jamieson, Dennis B. Gannon


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